Package-on-package got another endorsement last week when Nvidia said it would use 3-D packaging on some forthcoming Pascal graphics processors to make more memory available with minimal delays. The move comes as more industries are adopting the company’s parallel processing chips.
Nvidia President and CEO Jen-Hsun Huang made 3-D packaging one of the first highlighted technologies at the company’s annual GPU (graphics processing unit) Technology Conference. GPUs are now limited by power and pin count, he explained. A key factor for the pin limitation is that parallel processors require lots of bandwidth and wide data paths to large memory blocks.
Stacking memory chips will let the company provide lots of memory that can be accessed quickly. Huang noted that 3-D stacking will let the company “take bandwidth to new levels over the next two years.” Memory interfaces are migrating from hundreds of bits to thousands of bits, he added.
Memory chips will utilize through silicon vias. They will be stacked on wafers, so the distance from processors to memories will be minimal. Nvidia’s move marks a major step forward for package-on-package technologies. The company’s processors are no longer limited to video gaming and graphics. Military and automotive applications are just a couple of the industries that are moving to its GPUs. When a company that plays in both high-volume and high-reliability markets adopts a technology, it’s a good sign that technology is moving into the mainstream.
Filed under: electronics, Technical Tagged: 3-D packaging, memory interfaces, package on package, through silicon vias
