Getting multiple groups to work together often extends the time it takes to finish a project. But when IPC and JEDEC teamed up to create a standard for grid array package testing, they shortened the typical standard development cycle.
IPC/JEDEC-9706, Mechanical Shock In-situ Electrical Metrology Test Guidelines for FCBGA SMT Component Solder Crack and Pad Crater/Trace Crack Detection, was completed in 12 months. It’s one of many IPC standards that are being completed in shorter timeframes.
It didn’t hurt that the point people for the IPC and JEDEC committees were friends who worked in the same Intel facility. Ramgopal Uppalapati and Ife Hsu, who worked with the respective IPC and JEDEC committees, helped to develop the metrology technique. When questions arose from the committee members who turned the Intel-developed technology into a universal tool, they typically had the right answers.
Both groups worked on the technology simultaneously. The chairmen then pulled together the input from each committee. They say the simultaneous work prevented the zigs and zags that can occur when different groups take dissimilar paths.
The quick turnaround highlights IPC efforts to shorten development cycles. More work is being done remotely as volunteers leverage Web-based conferencing technologies. Uppalapati noted that IPC managers are very open to changes, which helps creative committee chairmen get the most from their committee members.
Filed under: Committees, IPC, Standards, Technical Tagged: grid array package testing, IPC/JEDEC-9706
