The fact that all technologies in a system are increasingly interconnected is one of the truisms of this era. As densities get finer, cost pressures increase and quality requirements rise, it’s critical that every aspect of a system work in harmony.
This trend is blurring the lines between semiconductors and packaging. That’s an interesting phenomenon to Phil Marcoux, president of PPM Associates. He has worked around circuit boards and chips since the days when surface mount was a new term, and he was always seen at IPC meetings back then. The last few years, he’s spent more time working with semiconductors, so appearances at IPC gatherings have been less frequent.
Changes in technology have brought him back into the packaging world and IPC activities. Chipmakers that previously didn’t think much about packaging find it of “paramount importance” as they move to increase densities by stacking chips inside a package, according to Marcoux.
When chips are stacked atop one another, through holes and array packaging come to the fore. EMS providers and board fabricators are familiar with these concepts, so they can easily migrate into multilayer silicon technology. Line widths are small, but many EMS suppliers are already flirting with these line widths, Marcoux said.
Decision makers throughout the packaging and interconnection worlds need to start thinking about how they can participate in this emerging area. Margins are certain to be higher than those in conventional products, and growth will be solid if not spectacular.
Companies throughout the supply chain can gain an edge by being involved during the formative days of this technology transition. Marcoux will be providing more details on the possibilities at the IPC Conference on Component Technology: Closing the Gap in the Chip to PCB Process, on September 10 in Chandler, Ariz.
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